TSMC remains the undisputed leader in the semiconductor market, even as Samsung attempts to consolidate its position. Naturally, demand for TSMC’s products is immense, and analysts now predict that the production capacity of its 3-nanometer process will almost reach its limit by next year.
Reports from the Gemini Commercial Times, citing JPMorgan, indicate that TSMC is navigating various obstacles to meet demand, such as re-purposing existing production lines initially designed for the 4nm norms. In particular, one such facility is expected to boost production by about 25,000 wafers per month, while others are reserved for TSMC’s novel N2 and A16 nodes. Furthermore, dormant N6 and N7 lines will be retooled to support 3nm production, enabling the manufacturer to produce an additional 5,000 to 10,000 wafers monthly. By the end of 2025, the monthly wafer production volume is likely to reach an astounding 160,000 units.
However, achieving this milestone necessitates the reconfiguration discussed earlier. The primary client driving this expansion is none other than Nvidia. It is noteworthy that future Vera Rubin accelerators will be manufactured using 3nm technology, which is largely why TSMC is upsizing production.
Furthermore, a JPMorgan supply chain analysis has revealed that to ensure timely delivery, some clients are willing to pay TSMC a significant premium. This increase can be as much as 50-100%, and such orders constitute a substantial share, reaching about 10% of the total. In these circumstances, TSMC’s gross margin already exceeds 60%.
Aside from Nvidia’s needs, the 3nm process represents a major advancement in semiconductor technology, offering improved power efficiency and increased performance, which is crucial for future AI technologies and high-performance computing (HPC). This technological leap is expected to further solidify TSMC’s market dominance.
